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				Summary The partners in this project have jointly developed a high-performance 24-bit DSP which is suitable for a multitude of applications, such as decoding the AC-3 Dolby standard for digital TV audio, voice compression, multi-channel echo-cancellation, digital beam forming, etc. This DSP has been fabricated and has been demonstrated in an AC-3 decoder application. The project partners have also been working on the development of low power design techniques aimed at achieving 25% power reduction over designs performed with our current cell-based IC design flow. These techniques are based on the exploitation of local don?t care conditions in multi-level logic circuits and gate resizing to achieve a net reduction in overall circuit power dissipation. A greedy algorithm for low power circuit node optimisation using local don?t care conditions has been developed and tested in a simulation environment with encouraging results. Objectives To apply the developed low power design techniques to the existing 24-bit DSP which is already fabricated To assess the merit of the mew techniques using experimental silicon through comparisons of the projected power reduction (in simulation) and actually measured reduction of new DSP; assessment of the commercial impact. Participants DCT-Hellas (Gr), Atmel/ES2 (F) Design Story Public Deliverables

   

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