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lpgd

lpgd

				Summary A top-down design methodology/flow is proposed for power reduction, emphasising on optimisations at the algorithmic and architectural levels with respect to area, time and power. The design flow includes global and local power optimisation techniques and transformations at each design level. At the algorithm level, alternatives are explored in respect of locality, complexity, parallelism, and loop transformations. At the architecture level, the switching activity problem of modules and their interconnections is reduced by techniques like power-down, memory management, clock distribution, and data representation in relation to the statistical features of input signals. At the logic level, further power optimisation may be achieved by reducing the switching activity of the nodes of a logic circuit, by technology mapping, or by multilevel logic transformations. The design flow will be described in a universal way, so that its integration and application to other Design Environments is possible. It will be demonstrated at the example of a GFSK/GMSK MODEM, one of the most critical blocks in the entire baseband signal processing of a multi-mode DCS1800-GSM/DECT terminal. Objectives To complete the development of a top-down, low power design methodology/flow for DSP applications. To demonstrate the methods at the example of an integrated GFSK/GMSK Modulator-Demodulator (MODEM) for DCS1800-GSM/DECT applications. Participants INTRACOM (GR); University of Patras (GR) Design Story Public Deliverables

   

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