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paprica

paprica

Summary

The PAPRICA project will demonstrate the capability of CMOS technology in the low power RF domain, to achieve a considerable power reduction in wireless terminals.

The main goal is to design a new architecture for RF digital mobile communication systems. The novel receiver architecture, called DOUBLE Quasi-IF (DQIF), offers a high degree of flexibility, allowing its implementation for a different number of standards, like DECT, PMR (TETRAPOL), and GSM. Since a relevant part of signal processing is performed at baseband instead of high frequency, the architecture offers a reduction in power consumption when compared with other traditional techniques, like the super-heterodyne one. Particular features are

triple RF to baseband down-conversion, with

first down conversion at 150 MHz through a LO at fixed frequency,

second conversion of a sub-band of 3 MHz containing the desired channel

third completely digital conversion after delta-sigma A/D conversion,

final channel selection performed in the digital domain.

Due to the particular conversion technique, the electrical specifications of the most critical blocks in the conversion stages will be less demanding, and consequently expected power consumption will be very competitive.

Results will be made available publicly through project 25213 TARDIS.

Objectives

Feasibility assessment of DQIF, through physical design and characterisation of the core blocks;

DQIF "ad-hoc" block specifications from system specifications (i.e. DECT, TETRAPOL);

Low-power RF design techniques in standard CMOS digital process;

Process qualification for RF (RF design Manual);

RF design tools and framework; PAPRICA Design Kit.

demonstration of a practical implementation of a specific application TETRAPOL

Participants

ATMEL ES2 (F), IST (P), Matra Nortel Communication (F)

Design Story

Public Deliverables