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				Summary In this programme the partners are studying and developing techniques for Low Power / Low voltage circuit operation with the aim of demonstrating in a practical form a reduction in typical system power demand through the application of new techniques and supply voltage reduction. The results will be demonstrated at the Viterbi element of the QPSK chip in the Mitel set-top box chip-set. In the first year, a number of approaches were investigated and assessed through modelling and simulation. The successful techniques will then be fabricated in silicon to compare the performance with the simulations and demonstrate the practical benefit of the selected power reduction strategies. When the new ideas have been proven and incorporated into the normal Mitel CAD design flows, next generation chips for the interactive TV market will be designed for European systems companies. The low power circuits will then be incorporated into other areas of the business to make maximum use of the developed techniques. With the University partners information on the results will be collected and disseminated throughout the ESD-LPD clusters and into third party organisations so the techniques will be of maximum benefit to European electronic systems companies. Results will be made available publicly through Project 25213 TARDIS. Objectives Survey of contemporary Low Power Design techniques and commercial power analysis software tools Investigation of architectural and algorithmic design techniques with a power consumption comparison Investigation of Asynchronous design techniques and Arithmetic styles Set-up and assessment of a low-power design flow Fabrication and characterisation of a Viterbi demonstrator to assess the most promising power reduction techniques Participants Mitel Semiconductor (UK), University Of Manchester (UK), Queens University, Belfast (UK) & University Of Sheffield (UK). Design Story Public Deliverables

   

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