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soflopo

soflopo

				Summary SOFLOPO will develop techniques and guidelines for mapping a specific algorithm code onto appropriate instruction subsets, so that it allows an optimal low-power code execution, for microprocessor architectures used in embedded applications. The power consumption of the code will be evaluated by means of physical measurements, instead of a detailed bottom-up simulation approach, which is unavailable due to the lack of detailed processor models. Upon these measurements, detailed models that relate software code and power dissipation will be established. These models will form the basis of developing code optimisation techniques for the purpose of low-energy software execution. Extensions of existing algorithms for Interpreter optimisation that will aim at energy minimisation will be developed. This systematic modelling of the relationship between power dissipation and software code will take place for the ARM-RISC processor. An extension of the above methodologies to include DSP processors will follow. These processors constitute a big portion of embedded microprocessors. Except from specific conclusions for each architecture under inspection, general conclusions, applicable to other architectures, within some accuracy limit, will be extracted. The viability of the derived techniques will be demonstrated by their application upon the implementation by DCT- Hellas of the IEEE 802.11 protocol microcode, used in Wireless Local Area Networks. For their full dissemination, the results of the SOFLOPO project will be integrated into software for the power-conscious ARM-RISC and DSP code optimisation. This software will be available to interested third parties. It will be also available for free to Universities under a non-disclosure agreement. Objectives Characterise the instruction set of the ARM (and a DSP) processor in terms of power consumption. establish models that relate software code and power dissipation. develop techniques and guidelines for mapping a specific algorithm code onto appropriate instruction subsets. integrate these techniques into software for the power-conscious ARM-RISC and DSP code optimisation. Participants University of Patras (GR), Data Communications Technologies-Hellas (GR) Design Story Public Deliverables

   

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