LOVO

Power electronics; low output voltage dc/dc converters for low power applications.

 PAPRICA

New algorithm/architecture for RF part of DECT/GSM, compatible with digital ATMEL process (analogue processing).

 SUPREGE 

Micropower transceiver architecture for short distance wireless communication (super-regenerative principle); applied to 3 demonstrators.

 SALOMON 

Techniques and tools to estimate power dissipation of high level analogue and digital blocks; applied to telecom examples.

 COOL-LOGOS

Power reduction through use of local "don't care" conditions and global state resizing; applied to a high performance 24-bit DSP.

 PCBIT

Use of power management schemes, gate level "pre-computation";low power ISDN interface for portable PCs.

 SOFLOPO

Software (compiler) optimisation for low power (for ARM and a DSP processor); estimate power consumption of program execution.

 PREST

Use of asynchronous design, efficient architecture and gate level design, to reduce power in a CMOS GSM chip set.

 LPGD

Power optimisations at algorithmic and architectural level; top down design flow; integrated GFSK/GMSK modem design.

 DESCALE

Asynchronous design ("handshake methodology") to reduce power and peak current, applied to smart card IC design.

 AMIED

Algorithm evaluation and architecture trade-offs; asynchronous design; design flow; encryption/decryption chip design.

 DAB-LP

Specification transformations to minimise access to large memories and distant data in DSP systems; applied to a DAB IC.

 COLOPODS

Low power/low voltage re-design of hearing aid DSP; architecture choice; pipelining; gated clock design, routing strategy.

 I-MODE

Design of analogue baseband filters and AD converters, based on current-mode principle; DECT/DCS1818 transceiver design.

 ALPINS

New architecture for design of low voltage log domain filters applied to DECT and GSM handset design.

 CRAFT

Design methodology for RF components for GSM/DECT; based on MOS transistor model for deep submicron and RF mode operation.

 MELOPAS

System simulation for analyses of power consumption of mixed mode ASICs; applied to a RISC processor.

 COSAFE

Development of an ASIC for safety critical applications, applied to infusion pump controller design.

 LUCS

Design of digital front-end for medical diagnostic ultrasound equipment.